An IEEE Cluster 2020 Workshop
This project is maintained by arm-hpc
Registration is free and open to all. Please click here to register
EAHPC-2020 will be running as a live, recorded event on Monday 14 September 2020. The dial-in details will be provided via the IEEE Cluster conference to registered attendees.
| Time | Title | Speaker |
|---|---|---|
| 08:00 – 08:10 | Organizer’s introduction | |
| 08:10 – 08:30 | Investigating applications on the A64FX | Adrian Jackson |
| 08:30 – 08:50 | Preliminary Performance Evaluation of the Fujitsu A64FX Using HPC Applications | Tetsuya Odajima |
| 08:50 – 09:10 | The Effects of Wide Vector Operations on Processor Caches | Andrei Poenaru |
| 09:10 – 09:20 | Short break | |
| 09:20 - 09:30 | On the usage of the Arm C Language Extensions for a High-Order Finite-Element Kernel | Guillaume Quintin |
| 09:30 – 09:50 | Porting Applications to Arm-based Processors | Bine Brank |
| 09:50 – 10:10 | CoreNEURON: performance and energy efficiency evaluation on Intel and Arm CPUs | Joel Criado |
| 10:10 – 10:30 | Performance evaluation of ParalleX execution model on Arm-based Platforms | Nikunj Gupta |
| 10:30 – 10:35 | Short break | |
| 10:35 - 11:00 | Discussions/Q&A/Concluding remarks |
The submission deadline has been extended by 1 week. Submission is now due 20th July Anywhere on Earth (AoE).
Submissions via EasyChair EAHPC-2020.
Due to COVID-19 this workshow will be hosted virtually.
As part of the IEEE Cluster 2020 conference we will host a 1/2 day Arm workshop on evaluating emerging, server-class, Arm technology.
The IEEE Cluster conference will be hosted this year between the 14th and 17th of September. The current plan is to go ahead with hosting it in Kobe, Japan. However, due to COVID-19, it is possible that the conference will be hosted virtually, including the workshops.
This workshop focuses on the porting and optimization of scientific and high-performance workloads to the Arm architecture. The last few years have seen an explosion of 64-bit Arm based processors targeted towards server and infrastructure workloads – often with a specialization towards a specific domain – such as HPC, cloud and machine learning.
Arm’s new Neoverse reference N1 core design has become the foundation for a number of emerging processors such as Amazon’s 64-core Graviton2 and Ampere’s 80-core Altra, with the EPI project incorporating the successor design into SiPearl’s Rhea chip. Further, architecture licenses are being exploited to design and manufacture bespoke solutions such as Marvell’s ThunderX line of processors and Fujitsu’s A64FX chip.
One of the most important additions to the Arm instruction set has been SVE – the Scalable Vector Extension – an architectural extension containing a comprehensive set of vector length agnostic vectorization instructions. Making its debut in the A64FX processor, these vector instructions present a paradigm shift for application developers.
In this workshop we invite papers on the porting and, if available, optimization of high-performance workloads to this new generation of Arm-based processors. We welcome performance optimization studies either through access to real hardware or via simulation/emulation frameworks, for both SVE and otherwise.
Content specifically focuses on HPC, Edge, and everything in between. Specifically, we will include talks related to applications and cross-over/emerging application areas such as machine learning, deep learning, bioinformatics, and analytics; all on Arm-compatible platforms.
This workshop is closely related to the series of workshops organized at ISC, SC and the Arm Research Summit, the Arm HPC User’s Group (AHUG).
Submissions will be taken through EasyChair at the following link: EAHPC-2020.
Accepted papers will be included in the IEEE Cluster 2020 conference proceedings.
All submissions must be made in IEEE Format.
John Linford (john.linford@arm.com)